Mixed Signal Circuit Design Lab.       Dept. of Electronic Engeering of Sogang Univ.


    Publications

    < International Journal Papers >

    [1]    C. Shin and G. Ahn, "A 10-bit 100-MS/s Dual-Channel Pipelined ADC Using Dynamic Memory Effect Cancellation Technique,"  Circuits and Systems II: Express Briefs, IEEE Transactions on, vol.58, pp.274-278, May 2011.

    [2]    G. Noh and G. Ahn, "A 2.5V 109 dB  DR ĥADC for Audio Application,"  Journal of Semiconductor Technology and Science, vol. 10, pp.276-281, Oct. 2010.

    [3]    H. Choi, P. Yoo, G. Ahn,and S. Lee, A 14b 150 MS/s 140 mW 2.0 mm2 0.13 um CMOS A/D converter for software-defined radio systems, International Journal of Circuit Theory and Applications, vol. 39, pp.135-147, Feb. 2011.

    [4]    M. Choi, G. Ahn and S. Lee, 12b 50 MS/s 0.18 um CMOS ADC with highly linear input variable gain amplifier,Electron Lett., vol. 46, no. 18, pp. 1254-1256, Sep. 2010.

    [5]    Y. Kim, H. Choi, G. Ahn, and S. Lee, A 12 bit 50 MS/s CMOS Nyquist A/D converter with a fully differential class-AB switched op-amp, IEEE J. Solid-State Circuits, vol. 45, no. 3, pp. 620-628, Mar. 2010.

    [6]    H. Choi, Y. Kim, G. Ahn, and S. Lee, A 1.2-V 12-b 120-MS/s SHA-free dual-channel Nyquist ADC based on midcode calibration, IEEE Trans. Circuits Syst. I, vol. 56, no. 5, pp. 894 - 901, May. 2009.

    [7]    M. Kim, G. Ahn, P. Hanumolu, S. Lee, S. Kim, S. You, J. Kim, G. Temes, and U. Moon, A 0.9V 92dB double-sampled switched-RC delta-sigma audio ADC, IEEE J. Solid-State Circuits, vol. 43, no. 5, pp. 1195-1206, May 2008.

    [8]    G. Ahn et.al., A 0.6V 82dB delta-sigma audio ADC using switched-RC integrators, IEEE J. Solid-State Circuits, pp. 2398-2407, Dec. 2005.

    [9]    J. Li, G. Ahn, D. Chang, and U. Moon, A 0.9V 12mW 5MSPS algorithmic ADC with 77dB SFDR, IEEE J. Solid-State Circuits, pp. 960-969, Apr. 2005.

    [10]    D. Chang, G. Ahn and U. Moon, Sub-1-V design techniques for high-linearity multistage/pipelined analog-to-digital converters, IEEE Trans. Circuits Syst. I, vol. 52, pp. 1 - 12, Jan. 2005.

     

    < International Conference Papers >

    [1]    J. Kim, T. Kwon, G. Ahn, Y. Kim, J. Kwon, "A ĥ ADC using 4-bit SAR type quantizer for audio applications ," International SoC Design Conference, pp. 73-75, Nov. 2011. 

    [2]    C. Shin, M. Yoon, K. Cho, Y. Kim, K. Kim, S. Lee, G. Ahn, "A 6.25 MHz BW 8-OSR fifth-order single-stage sigma-delta ADC," IEEE International Symposium on Circuits and Systems, pp.1117-1120, May. 2011. 

    [3]    S. Yoo, G. Noh, K. Kim, G. Ahn J. Lee, J. Lee, I. Choi, A 1.6V ҥ ADC for digital electret microphone, International SoC Design Conference, pp. 283-286, Nov. 2010.

    [4]    X. Jiang, J. Song, T. Brooks, J. Chen, V. Chandrasekar, F. Cheung, S. Galal, D. Cheung,  G. Ahn, and M. Bonu, A 10mW stereo audio CODEC in 0.13 um CMOS, IEEE Int. Solid-State Circuits Conf., pp. 82-83, Feb. 2010.

    [5]    B. Park, S. Ji, M. Choi, K. Lee, G. Ahn, and S. Lee, A 10b 100MS/s 25.2mW 0.18 um CMOS ADC with various circuit sharing techniques, International SoC Design Conference, pp. 329-332, Nov. 2009.

    [6]    Y. Kim, H. Choi, K. Lee, G. Ahn, S. Lee, J. Kim, K. Moon, M. Choi, K. Moon, H. Park, and B. Park, A 9.43-ENOB 160MS/s 1.2V 65nm CMOS ADC based on multi-stage amplifiers, IEEE Custom Int. Circuits Conf., pp. 271-274, Sep. 2009.

    [7]    M. Kim, V. Kratyuk, P. Hanumolu, G. Ahn, S. Kwon, and U. Moon, An 8mW 10b 50MS/s pipelined ADC using 25dB opamp, IEEE Asian Solid-State Circuits Conf., pp. 49-52, Nov. 2008.

    [8]    J. Carnes, G. Ahn, and U. Moon, A 1V 10b 60MS/s hybrid opamp-reset/switched-RC pipelined ADC, IEEE Asian Solid-State Circuits Conf., pp. 236-239, Nov. 2007.

    [9]   G. Ahn, M. Kim, P. Hanumolu, and U. Moon, A 1V 10b 30MSPS switched-RC pipelined ADC, IEEE Custom Int. Circuits Conf., pp. 325-328, Sep. 2007.

    [10]    M. Kim, G. Ahn, P. Hanumolu, S. Lee, S. Kim, S. You, J. Kim, G. Temes, and U. Moon, A 0.9V 92dB double-sampled switched-RC delta-sigma audio ADC, Dig. Symp. VLSI Circuits, pp. 200-201, Jun. 2006.

    [11]    G. Ahn, et.al., A 12b 10MS/s pipelined ADC using reference scaling, Dig. Symp. VLSI Circuits, pp. 272-273, Jun. 2006.

    [12]   G. Ahn et.al., A 0.6V 82dB delta-sigma audio ADC using switched-RC integrators, IEEE Int. Solid-State Circuits Conf., pp. 166-167, Feb. 2005.

    [13]   J. Li, G. Ahn, D. Chang and U. Moon, 0.9V 12mW 2MSPS algorithmic ADC with 81dB SFDR, Dig. Symp. VLSI Circuits, pp. 436 - 439, Jun. 2004.

    [14]   M. Kim, G. Ahn and U. Moon, An improved algorithmic ADC clocking scheme, IEEE Int. Symp. Circuits Syst., vol. 1, pp. 589 - 592, May 2004.

    [15]   D. Chang, G. Ahn, and U. Moon, A 0.9V 9mW 1MSPS digitally calibrated ADC with 75dB SFDR, Dig. Symp. VLSI Circuits, pp. 67 - 70, Jun. 2003.

     

    < Ph. D. thesis >

    [1]    G. Ahn, Design techniques for low-voltage and low-power analog-to-digital converters,Sept. 2005.

     

    < Award >

    [1]   â, 2011 2 23, 17ȸ Z ޸ũ , (λ 100), ޸ ȿ 10 Ʈ 100 MS/s ä A/D ȯ⡱

    [2]   , , 2010 12 16, 2010 11ȸ ѹα ݵü, (λ 300), " ڸũ ̽ȸ"

     


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